Semiconductor Silicon Wafers

What a semiconductor wafer is

A semiconductor wafer is a thin, near-perfect disc of single-crystal silicon on which chips are printed. It is the substrate for every integrated circuit: a foundry exposes circuit patterns onto it, etches and deposits layers on it, and finally cuts it into individual dies that go to packaging. This node covers wafers for chipmaking, not solar wafers. The two share a raw material, silicon, and almost nothing else: solar wafers are cut to make cells and sold by the gigawatt, while chip wafers are polished to extreme flatness, checked for defects and metal contamination, and qualified fab by fab and process by process before a foundry will buy them in volume.

Shanghai Silicon describes the quality bar in its filing: surface flatness, metal impurity content, epitaxial layer thickness uniformity and resistivity consistency are the key indicators, and they must meet the strict standards of different process nodes and platforms (2026 interim report, p. 10). It also notes that wafer customers certify suppliers over a long cycle because the wafer is a core consumable whose quality directly sets the limits of what the fab can make (p. 15).

How wafers are made

The dominant route is the Czochralski method: a seed crystal is pulled slowly from molten silicon to grow a single-crystal ingot, which is then sliced, ground, lapped and polished into wafers. Shanghai Silicon lists its mastered steps as Czochralski and magnetic-field Czochralski pulling, thermal field simulation, large-diameter ingot cutting, high-precision rounding, low-stress wire cutting, chemical etching, double-side grinding and polishing, edge polishing, cleaning and epitaxy, plus SOI fabrication (p. 16).

Three product types matter commercially. Polished wafers are the bare substrate. Epitaxial wafers add a thin, precisely doped silicon layer grown on top, which is what most logic and power devices are actually built in. SOI wafers add a buried oxide layer that isolates the device layer, used for radio frequency, power and silicon photonics parts. Youyan Silicon lists the same full chain in its own technology table: crystal growth thermal field design, doping and defect control, heat treatment and film growth, fine processing and cleaning, and float-zone growth for high-purity material (2026 interim report, p. 12).

Sizes split the market. 300mm wafers serve advanced logic and memory at the largest fabs. 200mm and smaller wafers serve mature-node logic, power devices, sensors and analogue chips, where the wafer is cheaper and the qualification bar is lower. The wafers from this node feed semiconductor foundries, which print the circuits on them.

Where China stands

China position is split by size. In 300mm, Shanghai Silicon is the domestic leader by a wide margin: Shanghai and Taiyuan capacity reached 1.0 million wafers a month by mid-2026, with 1.2 million planned by year end, and 300mm sales volume rose more than 90% in the first half (NSIG pp. 7, 12). Its named customers span TSMC, UMC, STMicroelectronics and Vishay abroad and SMIC, Hua Hong Grace, CR Micro, Yangtze Memory and ChangXin Memory at home (p. 11). But volume did not mean profit: 300mm prices were still at a cyclical low after falling through 2023 to 2025, so revenue rose less than 60% and the group loss widened to ¥965m (p. 7).

In 200mm and smaller, Youyan Silicon is the listed specialist, with 8-inch capacity at 300,000 wafers a month after a second-quarter expansion, focused on power device wafers and etch equipment materials (Youyan p. 10). Its 12-inch business is only an associate that lost ¥98.51m in the half, which shows how far behind the second tier is at the leading size (p. 21). The structural gap is in specifications, not tonnes: Shanghai Silicon itself lists heavily doped epitaxial products, low-oxygen high-resistivity wafers, argon-annealed wafers, high-pixel image sensor substrates and SOI wafers as areas where domestic supply still falls short (NSIG p. 11).

What to watch

SEMI data cited by Shanghai Silicon (2026 interim report) put global wafer shipments at 3,275 million square inches in the first quarter of 2026, up 13.1% year on year, with demand split between hot 300mm demand for AI logic and high-bandwidth memory and a slower recovery in automotive and industrial mature nodes (NSIG p. 11). Two things decide whether Chinese wafer makers convert that recovery into profit: whether 300mm prices recover from their 2023 to 2025 lows, and whether domestic fabs qualify Chinese wafers for the high-end specifications listed above instead of importing them.

Our view: wafers are the quietest bottleneck in the Chinese chip chain. Foundries get the attention, but a fab cannot run without qualified wafers, and qualification is slow, sticky and specific to each process. China has solved the 200mm problem and is scaling the 300mm problem, but the profit pool still sits with the suppliers who can pass the hardest qualifications, and on the evidence of the 2026 interim reports, that is still a work in progress.